#ifndef _XCLKREG_H_
#define _XCLKREG_H_

/* Definitions for the XYCOM XVME 203/293 counter module, which is used in 
   this system as an RCI clock device. */

/* Definitions for the counter/timer interface. */

#define VME_IPL_1		0x9	/* csr setting for various VME */
#define VME_IPL_2		0xa	/* interrupt levels */
#define VME_IPL_3		0xb
#define VME_IPL_4		0xc
#define VME_IPL_5		0xd
#define VME_IPL_6		0xe
#define VME_IPL_7		0xf

#define VME_IPL		VME_IPL_5	/* default IPL level */

/* -- Master mode register */

#define BCD_SCALER		0x8000	/* do scaler counting in BCD */
#define INC_DATAPTR  		0x4000	/* automatic inc. of data ptr */
#define BUS_16			0x2000	/* 16 bit data bus selected */
#define FO_OFF			0x1000	/* FOUT line disabled */

#define FO_DIV			0x0f00	/* FOUT divide field mask */

#define FO_DIV16		0x0000	/* FOUT divided by 16 */
#define FO_DIV1			0x0100	/* FOUT not divided */
#define FO_DIV2			0x0200	/* FOUT divided by 2 */
#define FO_DIV3			0x0300	/* FOUT divided by 3 */
#define FO_DIV4			0x0400	/* FOUT divided by 4 */
#define FO_DIV5			0x0500	/* FOUT divided by 5 */
#define FO_DIV6			0x0600	/* FOUT divided by 6 */
#define FO_DIV7			0x0700	/* FOUT divided by 7 */
#define FO_DIV8			0x0800	/* FOUT divided by 8 */
#define FO_DIV9			0x0900	/* FOUT divided by 9 */
#define FO_DIV10		0x0a00	/* FOUT divided by 10 */
#define FO_DIV11		0x0b00	/* FOUT divided by 11 */
#define FO_DIV12		0x0c00	/* FOUT divided by 12 */
#define FO_DIV13		0x0d00	/* FOUT divided by 13 */
#define FO_DIV14		0x0e00	/* FOUT divided by 14 */
#define FO_DIV15		0x0f00	/* FOUT divided by 15 */

#define FO_SRC			0x00f0	/* FOUT source field mask */

#define FO_SRC_S1		0x0010	/* FOUT source is SRC1 */
#define FO_SRC_S2		0x0020	/* FOUT source is SRC2 */
#define FO_SRC_S3		0x0030	/* FOUT source is SRC3 */
#define FO_SRC_S4		0x0040	/* FOUT source is SRC4 */
#define FO_SRC_S5		0x0050	/* FOUT source is SRC5 */
#define FO_SRC_G1		0x0060  /* FOUT source is GATE1 */
#define FO_SRC_G2		0x0070	/* FOUT source is GATE2 */
#define FO_SRC_G3		0x0080	/* FOUT source is GATE3 */
#define FO_SRC_G4		0x0090	/* FOUT source is GATE4 */
#define FO_SRC_G5		0x00a0	/* FOUT source is GATE5 */
#define FO_SRC_F1		0x00b0	/* FOUT source is scalar F1 */
#define FO_SRC_F2		0x00c0	/* FOUT source is scalar F2 */
#define FO_SRC_F3		0x00d0	/* FOUT source is scalar F3 */
#define FO_SRC_F4		0x00e0	/* FOUT source is scalar F4 */
#define FO_SRC_F5		0x00f0	/* FOUT source is scalar F5 */

#define CMP1_ENABLE		0x0008	/* comparator 1 enabled */
#define CMP2_ENABLE		0x0004	/* comparator 2 enabled */

#define TOD_DIV5		0x0001	/* time-of-day enabled, divide by 5 */
#define TOD_DIV6		0x0002	/* time-of-day enabled, divide by 6 */
#define TOD_DIV10		0x0003	/* time-of-day enabled, divide by 10 */

/* -- Counter mode register */

#define GATE_CTRL		0xe000	/* gate control field mask */

#define GATE_HTCNM1		0x2000	/* active high TCN-1 */
#define GATE_HLNP1		0x4000	/* active high level N + 1 */
#define GATE_HLNM1		0x6000	/* active high level N - 1 */
#define GATE_HLN		0x8000  /* active high level N */
#define GATE_LLN		0xa000	/* active low level N */
#define GATE_HEN		0xc000	/* active high edge N */
#define GATE_LEN		0xe000	/* active low edge N */

#define FALLING_EDGE		0x1000	/* count on falling edge */

#define SRC_SELECT		0x0f00	/* source selection field */

#define SRC_TCNM1		0x0000	/* from previous counter */
#define SRC_S1			0x0100	/* from line SRC1 */
#define SRC_S2			0x0200	/* from line SRC2 */
#define SRC_S3			0x0300	/* from line SRC3 */
#define SRC_S4			0x0400	/* from line SRC4 */
#define SRC_S5			0x0500	/* from line SRC5 */
#define SRC_G1			0x0600	/* from line GATE1 */
#define SRC_G2			0x0700	/* from line GATE2 */
#define SRC_G3			0x0800	/* from line GATE3 */
#define SRC_G4			0x0900	/* from line GATE4 */
#define SRC_G5			0x0a00	/* from line GATE5 */
#define SRC_F1			0x0b00	/* from scalar F1 */
#define SRC_F2			0x0c00	/* from scalar F2 */
#define SRC_F3			0x0d00	/* from scalar F3 */
#define SRC_F4			0x0e00	/* from scalar F4 */
#define SRC_F5			0x0f00	/* from scalar F5 */

#define SPGATE_ENABLE		0x0080	/* special gate enabled */
#define HOLD_RELOAD		0x0040	/* reload from load or hold register */
#define REPEAT_CNT		0x0020	/* count repeatedly */
#define BCD_CNT			0x0010	/* BCD counting instead of binary */
#define UP_CNT			0x0008	/* count up instead of down */

#define OUT_CTRL		0x0007	/* output field mask */

#define OUT_LOWIMP		0x0000	/* inactive, low impendence */
#define OUT_HTCP		0x0001	/* TCP, active high */
#define OUT_TOGGLE		0x0002	/* toggled output */
#define OUT_HIGHIMP		0x0004	/* inactive, high impendence */
#define OUT_LTCP		0x0005	/* TCP, active low */

/* -- status register */

#define OUTPUT5			0x20	/* state of output 5 */
#define OUTPUT4			0x10	/* state of output 4 */
#define OUTPUT3			0x08	/* state of output 3 */
#define OUTPUT2			0x04	/* state of output 2 */
#define OUTPUT1			0x02	/* state of output 1 */
#define BYTE_SET		0x01	/* byte select bit in data ptr */

/* -- data ptr register */

#define CNTR1			0x01	/* select counter 1 regs */
#define CNTR2			0x02	/* select counter 2 regs */
#define CNTR3			0x03	/* select counter 3 regs */
#define CNTR4			0x04	/* select counter 4 regs */
#define CNTR5			0x05	/* select counter 5 regs */
#define CNTRL			0x07	/* select control regs */

#define MODE_REG		0x00	/* counter mode register */
#define LOAD_REG		0x08	/* counter load register */
#define HOLD_REG		0x10	/* counter hold register */
#define HOLD_REGI		0x18	/* counter hold reg, auto inc */

#define ALARM_1			0x00	/* alarm 1 register */
#define ALARM_2			0x08	/* alarm 2 register */
#define MASTER_REG		0x10	/* master mode register */
#define STATUS_REG		0x18	/* status register */

/* -- command definitons */

#define ARM			0x20	/* arm counters */
#define LOAD			0x40	/* load counters */
#define LOAD_ARM		0x60	/* load and arm counters */
#define DISARM			0xc0	/* disarm counters */
#define SAVE			0xa0	/* save counters */
#define DISARM_SAVE		0x80	/* disarm and save counters */
#define SET_TOGGLE		0xe8	/* set toggle output */
#define CLEAR_TOGGLE		0xe0	/* clear toggle output */
#define STEP			0xf0	/* step counter */
#define LOAD_PTR		0x00	/* load data ptr */
#define ENABLE_SEQ		0xe8	/* enable data ptr sequencing */
#define DISABLE_SEQ		0xe0	/* disable data ptr sequencing */
#define ENABLE_BUS16		0xef	/* enable 16 bit data bus */
#define ENABLE_BUS8		0xe7	/* enable 8 bit data bus */
#define FOUT_OFF		0xee	/* enable FOUT line */
#define FOUT_ON			0xe6	/* disable FOUT line */
#define DISABLE_PREFETCH	0xf9	/* disable prefetch for write ops */
#define ENABLE_PREFETCH		0xf8	/* enable prefetch for write ops */
#define RESET_CNTRS		0xff	/* reset everything */

/* Definitions for the Universal Interrupt Controller chip */

/* -- command definitions */

#define RESET_ICTRL		0x00	/* reset everything */
#define CLEAR_IRMR_ALL		0x10	/* clear IMR and IRR */
#define CLEAR_IRMR		0x18	/* clear IMR and IRR bit */
#define CLEAR_MR_ALL		0x20	/* clear IMR */
#define CLEAR_MR		0x28	/* clear IMR bit  */
#define SET_MR_ALL		0x30	/* set IMR */
#define SET_MR			0x38	/* set IMR bit */

#define CLEAR_IR_ALL		0x40	/* clear IRR */
#define CLEAR_IR		0x48	/* clear IRR bit  */
#define SET_IR_ALL		0x50	/* set IRR */
#define SET_IR			0x58	/* set IRR bit */
#define CLEAR_IS_HIGH		0x60	/* clear highest priority ISR bit */
#define CLEAR_IS_ALL		0x70	/* clear ISR */
#define CLEAR_IS		0x78	/* clear ISR bit */
#define MODE			0x80	/* load mode bits 0:4 */
#define SELR			0xa0	/* load mode bits 5 & 6 */
#define SELR_ARM		0xa1	/* load mode bits 5 & 6 and set 7 */
#define SELR_DISARM		0xa2	/* load mode bits 5 & 6 and clear 7 */
#define SELW_IM			0xb0	/* select IMR for writing */
#define SELW_AC			0xc0	/* select ACR for writing */
#define VECTOR			0xe0	/* select vector for writing */

/* -- interrupt mode register bits (write only) */

#define ROTATING_MODE		0x01	/* rotating interrupt priority */
#define COMMON_INTR		0x02	/* use only one interrupt vector */
#define POLLED_MODE		0x04	/* disable interrupts */
#define HIGHEDGE_INTR		0x10	/* interrupt on rising edge */

/* -- status regsiter bits */
	
#define GROUP_INT		0x80	/* some interrupt is present */
#define CHIP_ENABLED		0x40	/* UIC chip is enabled */
#define ROTATING_STAT		0x20	/* rotating interrupt priority */
#define POLLED_STAT		0x10	/* interrupts disabled */
#define INTR_ARMED		0x08	/* interrupts are armed */

/* Device register map for the XVME 203/293 counter board */

struct xyclkdevice {
  	unsigned char unused1[1];
	unsigned char cntrA_data;
	unsigned char unused2[1];
	unsigned char cntrA_com;
	unsigned char unused3[1];
	unsigned char cntrB_data;
	unsigned char unused4[1];
	unsigned char cntrB_com;
	unsigned char unused5[1];
	unsigned char uic_data;				
	unsigned char unused6[1];
	unsigned char uic_com;
	unsigned char unused7[117];
	unsigned char csr;
	unsigned char unused8[3];
	unsigned char quadselA;
	unsigned char unused9[3];
	unsigned char quadselB;
	unsigned char unused10[886];
  };

#endif
