/*-=-=-=-=-=-=-=-=-=-=-=- RCCL/RCI Notice of Copyright -=-=-=-=-=-=-=-=-=-=-*
 *									    *
 *	Copyright (C) 1987, 1991 by John E. Lloyd.			    *
 *									    *
 *	Information on copyright permissions, as well as a complete	    *
 *	disclaimer of warranty, is given in the file COPYRIGHT.		    *
 *									    *
 *-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/

#ifndef _DRVJDEVICE_H_
#define _DRVJDEVICE_H_

struct drjreg {
	unsigned char icmd0;
	unsigned char csra;
	unsigned short bufa;
	unsigned char ibuf0;
	unsigned char csrb;
	unsigned short bufb;
	unsigned char icmd1;
	unsigned char csrc;
	unsigned short bufc;
	unsigned char ibuf1;
	unsigned char csrd;
	unsigned short bufd;
};

/* Interrupt Mode Commands. These commands are described in the 
    DRV11-J manual. They are entered by the driver into the icmd registers */

#define ICMD_RESET		0x00	/* reset everything */
#define ICMD_CLEAR_IRMR_ALL	0x10	/* clear IMR and IRR */
#define ICMD_CLEAR_IRMR		0x18	/* clear IMR and IRR bit */
#define ICMD_CLEAR_MR_ALL	0x20	/* clear IMR */
#define ICMD_CLEAR_MR		0x28	/* clear IMR bit  */
#define ICMD_SET_MR_ALL		0x30	/* set IMR */
#define ICMD_SET_MR		0x38	/* set IMR bit */
#define ICMD_CLEAR_IR_ALL	0x40	/* clear IRR */
#define ICMD_CLEAR_IR		0x48	/* clear IRR bit  */
#define ICMD_SET_IR_ALL		0x50	/* set IRR */
#define ICMD_SET_IR		0x58	/* set IRR bit */
#define ICMD_CLEAR_IS_HIGH	0x60	/* clear highest priority ISR bit */
#define ICMD_CLEAR_IS_ALL	0x70	/* clear ISR */
#define ICMD_CLEAR_IS		0x78	/* clear ISR bit */
#define ICMD_MODE		0x80	/* load mode bits 0:4 */
#define ICMD_SELR		0xa0	/* load mode bits 5 & 6 */
#define ICMD_SELR_ARM		0xa1	/* load mode bits 5 & 6 and set 7 */
#define ICMD_SELR_DISARM	0xa2	/* load mode bits 5 & 6 and clear 7 */
#define ICMD_SELW_IM		0xb0	/* select IMR for writing */
#define ICMD_SELW_AC		0xc0	/* select ACR for writing */
#define ICMD_VECTOR		0xe0	/* select vector for writing */

/* mode register bits defs for writing */

#define DRJMODE_ROTATING	0x01	/* rotating interrupt priority */
#define DRJMODE_COMMON		0x02	/* use only one interrupt vector */
#define DRJMODE_POLLED		0x04	/* disable interrupts */
#define DRJMODE_HIGHEDGE	0x10	/* interrupt on rising edge */

/* the same mode bits for reading from status register */
	
#define DRJSTAT_GINT		0x80	/* some interrupt is present */
#define DRJSTAT_EI		0x40	/* interrupts are enabled */
#define DRJSTAT_ROTATING	0x20	/* rotating interrupt priority */
#define DRJSTAT_POLLED		0x10	/* interrupts disabled */
#define DRJSTAT_ARMED		0x08	/* interrupts are armed */

/* csr control bits */

#define DRJCSR_RDY		0x80	/* usr device is ready */
#define DRJCSR_IE		0x02	/* enable interrupts (csra only) */
#define DRJCSR_DIR		0x01	/* direction (output) */

/* application protocol bits */

#define DRJ_HANDSHAKE	0x8000
#define DRJ_LISTEN	0x0800
#define DRJ_READ_READY	0x0400
#define DRJ_WRITE_READY	0x0200
#define DRJ_SIGNAL_ACK	0x0100

#define DRJ_INTERRUPT0	0x0001
#define DRJ_INTERRUPT1	0x0002

#define DRJ_SIGOUT		DRJ_HANDSHAKE
#define DRJ_SIGIN		DRJ_HANDSHAKE

#define DRJ_DEFAULT_BLOCKTIME	20	/* 20 milliseconds */

extern drjRead();
extern drjTestRead();
extern drjWrite();
extern drjTestWrite();

extern drjProbe();
extern drjAttach();
extern drjDetach();
extern drjSignal();

extern drjIoctl();



#endif
