#include <machine/asm_linkage.h>
#include <machine/psl.h>
#include <machine/param.h>
#include <machine/trap.h>
#include <machine/reg.h>

#include <machine/mmu.h>
#include <machine/pte.h>
#include <machine/enable.h>
#include <machine/cpu.h>

#define OS4	1

#include <rciext/assym.s>

	.global _wrapped_swapout
_wrapped_swapout:
	/* moved instruction here */	.skip	4
	b,a	_swapout+4
	.empty

	.global _wrapped_hardclock
_wrapped_hardclock:
	/* moved instruction here */	.skip	4
	b,a	_hardclock+4
	.empty

	.global _wrapped_trap
_wrapped_trap:
	/* moved instruction here */	.skip	4
	b,a	_trap+4
	.empty

	.global _wrapped_syscall
_wrapped_syscall:
	/* moved instruction here */	.skip	4
	b,a	_syscall+4
	.empty

	ENTRY(onIntstack)
	set	eintstack, %o0
	cmp	%sp, %o0
	bgu	1f
	.empty
	set	intstack, %o0
	cmp	%sp, %o0
	blu	1f
	.empty
	set	1, %o0
	retl
	nop
1:	
	clr	%o0
	retl
	nop

	ENTRY(setcontext)
	set	CONTEXT_REG, %o1
	retl
	stba	%o0, [%o1]ASI_CTL	! write the context register

	ENTRY(getcontext)
	set	CONTEXT_REG, %o1
	retl
	lduba	[%o1]ASI_CTL, %o0	! read the context register

	.reserve	_rci_ipllock,4,"data",4

	ENTRY(lockipl)
	set	_rci_ipllock, %g1
	set	1, %o0
	st	%o0, [%g1]
	retl
	nop

	ENTRY(unlockipl)
	set	_rci_ipllock, %g1
	clr	%o0
	st	%o0, [%g1]
	retl
	nop

#define SETPRI(level) \
	set	_rci_ipllock, %g1; \
	ld	[%g1], %o0; \
	tst	%o0; \
	bz	1f; \
	mov	%psr, %o0; \
	retl; \
	nop; \
1: \
	andn	%o0, PSR_PIL, %g1; \
	or	%g1, (level << PSR_PIL_START), %g1; \
	mov	%g1, %psr; \
	nop; \
	retl; \
	nop;

	ENTRY(splzs)
	SETPRI(12)

	ENTRY2(spl7,splaudio)
	SETPRI(13)

	ENTRY(spl8)
	SETPRI(15)

	ENTRY2(spl6,spl5)
	SETPRI(10)

	ENTRY2(splbio,spltty)
	SETPRI(10)

	ENTRY(spl4)
	SETPRI(8)

	ENTRY(spl3)
	SETPRI(6)

	ENTRY(spl2)
	SETPRI(4)

	ENTRY(spl1)
	SETPRI(2)

	ENTRY(spl0)
	SETPRI(0)

	ENTRY(splx)
	set	_rci_ipllock, %g1
	ld	[%g1], %g2
	tst	%g2
	bz,a	1f
	and	%o0, PSR_PIL, %g1
	mov	%psr, %o0
	retl
	nop
1:
	mov	%psr, %o0
	andn	%o0, PSR_PIL, %g2
	or	%g2, %g1, %g2
	mov	%g2, %psr
	nop
	retl
	nop
