/*
 * pti.h  -  register definitions for PTI PT-SBS915 SBus to VME Adapter
 */

typedef unsigned char byte;

/* address offsets for registers and VMEbus access maps */ 
#define PTI_REG_OFFSET  0x0200000
#define PTI_MAP1        0x0400000
#define PTI_MAP2        0x0800000
#define PTI_MAP3        0x0c00000
#define PTI_MAP4        0x1000000
#define PTI_MAP5        0x1400000
#define PTI_MAP6        0x1800000
#define PTI_MAP7        0x1c00000
 
#define	PTI_NAME	"pti"
#define	DEFAULT_SLOT	2
 
/*
 * Register structure
 */
 
struct pti_reg { byte sem[8];     /* Semaphore Registers 0-7                */
		 byte na0[8];     /* unused */
   /* 0x10 */	 byte gpbyte0;    /* General Purpose Byte Register 0        */
		 byte gpbyte1;    /* General Purpose Byte Register 1        */
		 byte map1a;      /* VME Map 1 configuration     (1st byte) */
		 byte map1b;      /* VME Map 1 configuration     (2nd byte) */
		 byte map2a;      /* VME Map 2 configuration     (1st byte) */
		 byte map2b;      /* VME Map 2 configuration     (2nd byte) */
		 byte map3a;      /* VME Map 3 configuration     (1st byte) */
		 byte map3b;      /* VME Map 3 configuration     (2nd byte) */
   /* 0x18 */    byte map4a;      /* VME Map 4 configuration     (1st byte) */
		 byte map4b;      /* VME Map 4 configuration     (2nd byte) */
		 byte map5a;      /* VME Map 5 configuration     (1st byte) */
		 byte map5b;      /* VME Map 5 configuration     (2nd byte) */
		 byte map6a;      /* VME Map 6 configuration     (1st byte) */
		 byte map6b;      /* VME Map 6 configuration     (2nd byte) */
		 byte map7a;      /* VME Map 7 configuration     (1st byte) */
		 byte map7b;      /* VME Map 7 configuration     (2nd byte) */
   /* 0x20 */    byte rmwc;       /* Read/Modify/Write Control              */
		 byte s2vctrl;    /* SBus to VME Control Register           */
		 byte vmewina;    /* VME Window Address Register (1st byte) */
		 byte vmewinb;    /* VME Window Address Register (2nd byte) */
		 byte svaddra;    /* SBus Virtual Address Reg.   (1st byte) */
		 byte svaddrb;    /* SBus Virtual Address Reg.   (2nd byte) */
		 byte v2sctrl;    /* VME to SBus Control Register           */
		 byte leds;       /* Switch/LED Register                    */
   /* 0x28 */	 byte virqstat;   /* VME Interrupt Request Status           */
		 byte ivec1;      /* VME Interrupt Level 1 Vector           */
		 byte ivec2;      /* VME Interrupt Level 2 Vector           */
		 byte ivec3;      /* VME Interrupt Level 3 Vector           */
		 byte ivec4;      /* VME Interrupt Level 4 Vector           */
		 byte ivec5;      /* VME Interrupt Level 5 Vector           */
		 byte ivec6;      /* VME Interrupt Level 6 Vector           */
		 byte ivec7;      /* VME Interrupt Level 7 Vector           */
   /* 0x30 */    byte virqctrl;   /* VME Interrupt Request Control Register */
		 byte sbusirq;    /* SBus Interrupt Request Select Register */
                 byte sbusctrl;   /* General SBus Control Register          */
	       };


/* useful (?) macros */
/* PTI_SET_AMAP() takes a 32bit address, a VME mode, and puts the appropriate
   bits in the two map configuration registers supplied */
#define PTI_SET_AMAP(addr, mode, reg1, reg2) \
  ( (reg1) = (((addr)>>24) & 0xff),          \
    (reg2) = ((((addr)>>22) & 0x03)<<6) | ((mode)&0x3f))


/* Register Bit Definitions */

#define VME16    0x29          /* VME Access Modifiers */
#define VME16_SU 0x2D
#define VME24    0x39
#define VME24_SU 0x3D
#define VME32    0x09
#define VME32_SU 0x0D

/* Bit definitions for SBus To VME Control Register (s2vctrl) */
#define BR0 0x00                 /* VME Bus Request Levels */
#define BR1 0x01
#define BR2 0x02
#define BR3 0x03
#define ROR 0x04                 /* Release On Request   */
#define RBC 0x08                 /* Release on Bus Clear */
#define HOG 0x10                 /* Hold VMEbus regardless of RGC/ROR flags */
#define OWN 0x20                 /* Do we own the VMEbus? (r/o) */
#define VSR 0x80                 /* Reset the VMEbus */


/* Bit definitions for VME To SBus Control Register (v2sctrl) */
#define V2S_ENAB   0x20
#define V2S_DISAB  0x00
#define V2S_AMOD32 0x10
#define V2S_AMOD24 0x00
#define V2S_128K   0x00
#define V2S_256K   0x01
#define V2S_512K   0x02
#define V2S_1M     0x03
#define V2S_2M     0x04
#define V2S_4M     0x05
#define V2S_8M     0x06
#define V2S_16M    0x07
#define V2S_32M    0x08
#define V2S_64M    0x09
#define V2S_128M   0x0a
#define V2S_256M   0x0b
#define V2S_512M   0x0c
#define V2S_1G     0x0d
#define V2S_2G     0x0e
#define V2S_4G     0x0f


/* Bit definitions for VME Interrupt Request Control Register (virqctrl) */
/*                 and VME Interrupt Request Status  Register (virqstat) */
#define VIRQ7 0x80
#define VIRQ6 0x40
#define VIRQ5 0x20
#define VIRQ4 0x10
#define VIRQ3 0x08
#define VIRQ2 0x04
#define VIRQ1 0x02
#define VFAIL 0x01


/* Bit definitions for the Switch/LED Register (leds) */
#define LED0 0x01
#define LED1 0x02
#define LED2 0x04
#define LED3 0x08
#define SW0  0x10
#define SW1  0x20
#define SW2  0x40
#define SW3  0x80
